module simctl(
        input           i_wb_clk,
        input           i_wb_rst,
        input           i_wb_cyc,
        input           i_wb_stb,
        input           i_wb_we,
        output          o_wb_ack,
        input   [ 2:2]  i_wb_adr,
        input   [ 3:0]  i_wb_sel,
        input   [31:0]  i_wb_dat,
        output  [31:0]  o_wb_dat
);

wire    [ 7:0]  r0;
reg     [31:0]  wb_dat_o;

wb_ack u_wb_ack(
        .CLK_I(i_wb_clk),
        .RST_I(i_wb_rst),
        .CYC_I(i_wb_cyc),
        .STB_I(i_wb_stb),
        .ACK_O(o_wb_ack)
);

// [0] RW simulation state; simulation is terminated when written to
// [4]  W output channel

always @(posedge i_wb_clk) begin
        if (i_wb_cyc & i_wb_stb) begin
                wb_dat_o <= i_wb_adr ? 32'b0 : {24'b0, r0} ;
`ifndef SYNTHESIS
                if (i_wb_we) begin
                        if (~i_wb_adr & i_wb_sel[0]) begin
                                $finish;
                        end else
                        if ( i_wb_adr & i_wb_sel[0]) begin
                                $write("%c", i_wb_dat[7:0]);
                        end
                end
`endif
        end
end

`ifndef SYNTHESIS
assign r0 = 8'b1;
`else
assign r0 = 8'b0;
`endif

assign o_wb_dat = wb_dat_o;

endmodule
